1. Field of the Invention
Embodiments of the invention generally relate to a metallization process for manufacturing electronic and semiconductor devices, more particularly, embodiments relate to methods for depositing and treating cobalt films on a substrate.
2. Description of the Related Art
Currently, cobalt is a metal of choice for use in multilevel metallization processes that are crucial to device manufacturing, especially for the PMOS work function layers of metal-oxide-semiconductor field-effect transistor (MOSFET) as well as wetting layer for direct metal gap fill. The multilevel interconnect features that drive the manufacturing processes have high aspect ratio apertures including contacts, vias, lines, gaps, and other features. Filling these features without creating voids or deforming the feature geometry is more difficult when the features have higher aspect ratios. Reliable formation of interconnects is also more difficult as manufacturers strive to increase circuit density and quality.
As the use of cobalt has permeated the marketplace due of a relative low cost and processing properties, manufacturers of semiconductor, solar, and other electronic devices continue to look for ways to increase conductivity while improving surface roughness of the cobalt layer and improving the boundary regions between cobalt and other material layers by reducing cobalt diffusion and agglomeration. Several processing methods have been developed to manufacture interconnects containing cobalt as feature sizes have decreased. Each processing method may increase the likelihood of problematic issues such as cobalt conductivity, cobalt crystalline structure deformation, and agglomeration. Physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electrochemical plating (ECP), electroless deposition, and other deposition techniques have been utilized for depositing cobalt materials and layers, however, such cobalt layers generally suffer with the aforementioned issues.
A cobalt layer deposited by a CVD or ALD process generally has greater electrical resistivity relative to a similar cobalt layer deposited by a PVD process. Generally, the greater resistivity is due in part to a significant carbon content (e.g., about 5 atomic percent) as well as a high surface roughness of the thin cobalt layer deposited by a CVD or ALD process. Such high carbon contents and surface roughness significantly impact the work function of the cobalt layer as a p-type metal and generally causes a high resistance of the overall integrated gate stack or other device the cobalt layer is contained therein. Cobalt layers deposited by PVD are often non-conformal and have other irregularities that affect device performance and stability. Also, high aspect ratio features usually develop voids during the deposition of cobalt materials by PVD or CVD. Non-vapor deposition processes for cobalt, such as ECP and electroless, generally require exposing the substrate and all layers thereon to a liquid bath, such as an aqueous solution, while depositing the cobalt layer thereon. Also, the cobalt layers deposited by ECP and electroless deposition processes may often have relative high resistivity and poor conformal films.
Therefore, a need exists for a method for forming cobalt layers, films, and materials and for devices containing such cobalt layers, films, and materials.